Electronic substrate technology is one of the most important enabling technologies for packaging and 3D integration of microelectronics. Typical electronic substrates are made from organic materials or thin silicon wafers that have vertical holes created within them, which are then filled with a suitable conductor such as metal. These conductive vertical interconnects are known as “vias.” These electronic substrates are then used to connect one electronic circuit to another by stacking them. In microelectronic packaging, the electronic substrate is typically used to connect a microelectronic chip to a printed circuit board. In addition, the electronic substrate may be used to connect one microelectronic chip to another by stacking the first chip on top of the second. When used in microelectronic chip stacking, the electronic substrate is referred to as an “interposer”. Conventional interposers are made from silicon which can produce somewhat high densities of vias, but are very expensive and difficult to build, requiring special etching and plating steps. Due to the limitations of the deep etch process, conventional silicon fabrication processes typically cannot produce via openings that are closer than approximately 40 microns, resulting in a limited pitch density for interconnects.
Most interposers or electronic substrates for chip-to-chip connections are made from thin silicon wafers that have vertical holes deep etched within them that are then filled with a suitable metal such as copper. These vertical vias are sometimes called “thru-silicon vias” or TSV). These passive silicon interposers are then used to connect one microelectronic chip to another by stacking them between microelectronic chips. Silicon interposers with TSVs offer a way for designers to achieve the benefits of chip-scale connected configurations, allowing compact integration of different microelectronic devices in a single package. The use of a silicon interposer is often referred to as a 2.5D-IC. [Hogan 2011].
A typical interposer application is illustrated in FIG. 1. In this configuration, a printed circuit substrate (101) is prepared with solder connections (103) to a package substrate (105). The package substrate (105) contains micro connections (107), such as a ball grid array, which make electrical contact to a dielectric interposer (109), having a plurality of metal filled vertically conducting vias (111) which make electrical contact between the bottom and top. A redistribution layer (RDL) (113) on the surface of the interposer (109), which makes electrical contact to the contact pads (115) of integrated circuit chips connected to the top of the RDL (113).
Silicon interposers are very expensive and difficult to make, requiring the use of high end etching tools such as deep reactive ion etch [Laermer 1996], and careful electrodeposition of metal into the etched holes. The main elements of a 3D Si interposer typically include front-side multi-level metallization (MLM), TSVs, and one or more layers of backside metallization. The MLM is sometimes referred to as a redistribution later (RDL) [Malta 2010].
Certain films, when electrochemically processed, produce highly vertical nanopores through the film thickness. Electrochemically etched silicon and electrochemically oxidized aluminum both exhibit this feature. Anodic aluminum oxide (AAO) is particularly attractive for interposer applications since the starting material (aluminum) is inexpensive, the process is relatively straightforward, and the resulting oxide layer is both strong and highly non-conductive. When anodized properly, AAO exhibits nanoporous structure having highly vertical nanopores extending from the top surface to the bottom layer of the AAO. An example of a deep AAO film is shown in FIG. 2, which shows a scanning electron microscope (SEM) image of a cross section of the AAO film. The film is grown from a base layer of aluminum (201). The film (203) itself consists of anodized aluminum oxide, having vertical pores, which are readily seen in the image, extending from the base to the top surface (205) of the film (203).
Work in the early 2000's demonstrated that vertically grown conductive nanowires in anodized aluminum oxide (AAO) could be used as interposers for chip stacking applications [Lin 2005]. In these devices, a foil or sheet of aluminum is electrochemically anodized (typically twice) to produce a high density of vertically aligned pores (as seen in FIG. 2), often arranged in a honeycomb pattern. Conductive material such as silver or copper is electroplated in these holes to produce a large number of vertically aligned metal nanowires, each wire separated by insulating AAO walls (this process is referred to as nanowire growth in AAO templates). The top and bottom surface of the foil is etched and polished to reveal a thin foil of vertically aligned conductive nanowires. Typical thickness of the foil is 50 microns, which is an appropriate thickness for interposer applications. Since the wires are all vertically aligned and insulated from each other, electrical current can only flow in the vertical direction (z-direction), not in the lateral direction. Researchers have reported electrical resistance from top surface to bottom surface of less than 0.2 ohms, whereas lateral resistance has been reported as greater than 4 Gigaohms [Lin 2005].
Despite initial positive results, interposers made from vertically aligned nanowires have not been commercially successful. The electroplating operation to fill the nanopores is quite time intensive. Furthermore, the existence of so many metal wires surrounding the vias of interest produce a significant amount of capacitive coupling, resulting in loss of signal and cross talk between connections, especially at high frequencies. In addition, the high metal content of the AAO substrate results in excessive stress in the material during thermal cycling.
Many electronic substrates are used for chip-to-printed circuit connections. In these applications, a microelectronic chip is packaged using a hard material (such as epoxy) to protect the fragile chip, and the electronic substrate forms the bottom part of the package, allowing electrical connection between the protected chip and the external printed circuit board. These electronic substrates are called “package substrates” and are typically made from thin organic laminates (FIG. 1, package substrate (105)). Organic laminates typically use drilling or laser etching to produce vertical vias, and are typically unsuitable for producing vias that are very small in diameter or very close together. Such laminates can support holes that are typically no closer than 70 microns apart.
Electronic substrates made from organic laminates are typically made containing via structures that have circular cross section and are metal plated. However, there are many cases where a non-circular, complex cross section openings would be of value. Examples include areas for producing precise response for radio-frequency (RF) and microwave signals, for controlling capacitance or inductance of the package assembly, for providing a heat-sink, or for enabling fluid flow to occur within the package. In addition, organic substrates may not be suitable for carrying high frequency signals. Special conducting structures and low loss dielectrics would be beneficial for carrying high frequency signals through the substrate.
Therefore, it is desirable to provide a low cost, high resolution alternative to conventional organic package substrate technologies that can produce high density, highly vertical conducting vias of arbitrary cross section. This electronic substrate or interposer would be of great value for modern, high density, high power microelectronic packaging and for RF and microwave electronic devices.